Wang, Zhoukun (2009) Design and Multi-Technology Multi-objective Comparative Analysis of Families of MPSOC. PhD thesis Micro et Nano-Electronique, Unité d'Électronique et Informatique p.180.

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Abstract

Multiprocessor system on chip (MPSOC) have strongly emerged in the past decade in communication, multimedia, networking and other embedded domains. MPSOC became a new paradigm of high performance embedded application design. This thesis addresses the design and the physical implementation of a Network on Chip (NoC) based Multiprocessor System on Chip. We studied several aspects at different design stages: high level synthesis, architecture design, FPGA implementation, application evaluation and ASIC physical implementation. We try to analysis and find the impacts of these aspects for the MPSOC’s final performance, power consumption and area cost. We implemented a NoC based 16 processors embedded system on FPGA prototyping. Three NoCs provide different functionalities for sixteen PE tiles. We also demonstrated the use of our performance monitoring system for software debugging and tuning. With the bi-synchronous FIFO method, our GALS architecture successfully solves the long clock signal distribution problem and allows that each clock domain can run at its own clock frequency. On the other hand we successfully implemented AES and TDES block cipher cryptographic algorithms on this platform and results show linear speedup in computation time. The network part of our architecture has been implemented on ASIC technology and has been explored with different timing constraints and different library categories of STmicroelectronics’ 65nm/45nm technologies. The experimental results of ASIC and FPGA are compared, and we inducted the discussion of technology change impact on parallel programming.

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Table of content

Version française 18

Chapter 1 Introduction 36

1.1 Select MPSoC as the direction of thesis 36

1.2 Identify the MPSOC design and implementation issues 39

Chapter 2 State of the Art of Multiprocessor system on chip and Network on Chip 41

2.1 Introduction 41

2.2 Academic and Commercial MPSoC 41

2.3 Academic and Commercial NOCs 45

2.3.1 SPIN. 45

2.3.2 ÆTHEREAL 46

2.3.3 Nostrum 49

2.3.4 MANGO 51

2.4 Case study: Arteris Technology 52

2.5 Conclusion 54

Chapter 3 MPSOC Design and Implementation 56

3.1 Introduction of MPSOC and NoC Design 56

3.2 MP3NOC: A Family of Architectures 57

3.2.1 Generic Architecture 57

3.2.2 Architecture overview 59

3.2.3 Processing Element TILE 60

3.2.4 Network on Chip 63

3.2.4.1 OCP Network Interface Unit: 65

3.2.4.2 Switch: 66

3.2.4.3 DATA NOC 67

3.2.4.4 Synchronization NOC 68

3.2.4.5 Service NOC 71

3.3 Bi-Synchronous FIFO in GALS architecture 72

3.4 Performance Monitoring 74

3.4.1 Performance Monitoring system evaluation 76

3.5 Implementation 81

3.6 Conclusion 84

Chapter 4 MPSoC Performance Evaluation 85

4.1 Using encryption as evaluation application 85

4.2 The algorithm 86

4.2.1 The AES (Advanced Encryption Standard) 87

4.3 Operation Mode 89

4.3.1 TDES Parallelization 91

4.3.2 Data parallelization approach 91

4.3.2.1 Design Description 91

4.3.2.2 Timing and memory access schemes 94

4.3.3 Pipelined approach 95

4.3.3.1 Design description 95

4.3.3.2 Timing and memory access scheme 97

4.4 Results and Discussion 97

4.5 Conclusion 105

Chapter 5 MPSOC ASIC Design 106

5.1 MPSoC ASIC Design Introduction 106

5.2 standard cell ASIC design 107

5.3 ASIC 65nm and 45nm Semiconductor 108

5.4 ASIC Design Flow 109

5.5 MPSoC implementation case study 110

5.5.1 ASIC implementation of OCN 111

5.5.2 Backend design flow of our OCN ASIC implementation 112

5.6 switch ASIC synthesis results vs placement and route results 119

5.7 Design Space Exploration 123

5.7.1 ASIC Power vs Clock Frequency 123

5.7.2 ASIC Area vs Clock Frequency 126

5.7.3 FPGA-ASIC exploration 128

5.8 NoC and switch opportunities with technologies change: impact on parallel software programming portability 130

5.9 Conclusion 131

Chapter 6 Potential use of High level synthesis in MPSoC platform 133

6.1 Design Productivity and High Level synthesis 133

6.2 Embedded Processor Coprocessing Support 135

6.2.1 C-Based Synthesis and Hardware Accelerator Design Workflow 137

6.3 State of the art of c-based synthesis 139

6.4 SoC methodology of C-based synthesis 140

6.4.1 C-Language Fundamentals 140

6.4.2 HLS Approaches and Tools 141

6.5 Exploration of C-based synthesis of coprocessor design 145

6.5.1 Designs examples 146

6.5.2 Target Platform 149

6.5.2.1 Target technology 149

6.5.2.2 Tools and Options Combinations 151

6.6 Results of synthesis and place & route. 151

6.6.1 Area results 153

6.6.2 Variability of results with compilation options 154

6.7 Discussion 159

6.8 Design Space Exploration Coprocessors in MPSOC 161

6.9 Conclusion 163

Chapter 7 Conclusion 165

REFERENCES 170

PUBLICATIONS 179

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